A conventional technique in this field is disclosed in Technical Paper of the Institute of Electronics, Information and Communication Engineers of Japan, 89n[67] (1989-6-2), Koike, et al "55 ns 16 Mb DRAM with Built-in-Self-Test Function Using Micro-Program ROM", pp. 79-80.
As described in this publication, the memory size of a semiconductor memory device, e.g., a dynamic RAM of a large capacity, is small, so the breakdown voltage of the transistor forming the cell array is low. To improve the reliability, the power source voltage V.sub.CC (e.g., 5 V) needs to be lowered. Accordingly, use is made of a power source supply control section which produces, from the externally-supplied power source voltage (primary or main power source voltage) V.sub.CC an internal (secondary or auxiliary) power source voltage V.sub.D (e.g., 3.3 V), which is then used for driving the memory cell array. An example of such a dynamic RAM is shown in FIG. 2.
FIG. 2 is a circuit diagram of the pertinent portion of the conventional semiconductor memory device.
The semiconductor memory device is a dynamic RAM, comprising a memory cell array section 10, and a power source supply control section 60 for supplying a drive voltage to the memory cell array 10.
The memory cell array section 10 comprises a data storage memory cell section 20, a transfer gate section 30 for transferring data of the memory cell section 20, a sense amplifier section 40 for sensing and amplifying a minute read voltage from the memory cell section 20, and a column decode section 60 for selecting the output of the sense amplifier section 40.
In the memory cell section 20, a plurality of memory cells (only two of them, 21.sub.i, 21.sub.i+1, being illustrated) are disposed in a matrix arrangement, at intersections of a plurality of pairs of bit lines, such as BL, BL, a plurality of word lines, such as WL.sub.i, WL.sub.i+1. The memory cells 21.sub.i, 21.sub.i+1 and so on are formed of MOS transistors having a short gate length, so it is made to operate on an internal or auxiliary power source voltage V.sub.D (e.g., 3.3 V) of a lower level than the main power source V.sub.CC (e.g., 5 V).
The transfer gate section 30 is comprised of a plurality of pairs of n-channel MOS transistors (hereinafter referred to as NMOSTs) 31, 32 and so on, and which are turned on and off on the basis of a control signal TG to couple or isolate the pairs of bit lines BL, BL, etc. and the pair of sense amplifier nodes SA, SA, etc. The drains of the NMOSTs 31 and 32 are connected to the bit lines BL, BL, and their sources are connected to the sense amplifier nodes SA, SA, and their gates are commonly connected to receive the control signal TG.
The sense amplifier section 40 is comprised of a plurality of p-channel sense amplifiers 41 and so on, and n-channel sense amplifiers 42 and so on, connected to the respective pairs of bit lines BL, BL.
For instance, the p-channel sense amplifiers 41 are comprised of two p-channel MOS transistors (hereinafter referred to as PMOSTs) 41a and 41b. The PMOST 41a has its drain connected to the sense amplifier node SA, its source connected to sense amplifier drive common node PS, and its gate connected to the sense amplifier node SA. The PMOST 41b has its drain connected to the sense amplifier node SA, its source connected to the common node PS, and its gate connected to the sense amplifier node SA.
The n-channel sense amplifiers 42 are comprised of two n-channel MOSTs 42a and 42b. The NMOST 42a has its drain connected to the sense amplifier node SA, its source connected to sense amplifier drive common node NS, and its gate connected to the sense amplifier node SA. The PMOST 42b has its drain connected to the sense amplifier node SA, its source connected to the common node NS, and its gate connected to the sense amplifier node SA.
The column decode section 50 comprises a plurality of pairs of NMOSTs 51, 52 for connecting and disconnecting the pairs of the sense amplifier nodes SA, SA and so on, and the pairs of data lines DB, DB and so on, and their gates are controlled by the column decoder output signal CL.
The power source supply control section 60 comprises a current mirror amplifier 70 serving as a comparing and amplifying means, and PMOST 80 and NMOST 81 serving as a power source supply means.
The current mirror amplifier 70 is activated by a control signal PAS, and compares and amplifies the voltage on the p-channel sense amplifier drive common node PS and a reference voltage V.sub.R of the same level as the auxiliary power source voltage V.sub.D. It is comprised of two PMOSTs 71 and 72, and three NMOST 73, 74 and 75. The PMOST 80 serving as the power supply means has its drain and source respectively connected to the main power source voltage V.sub.CC and the common node PS, and its gate connected to the output of the amplifier 70. The NMOST 81 has its drain and source connected to the ground potential V.sub.SS and the n-channel sense amplifier drive common node NS, and its gate connected to receive the control signal PAS.
The operation of the circuit shown in FIG. 2 is described with reference to FIG. 3.
The read operation in which the memory cell 21.sub.i is selected is as follows:
First, at time t0, the word line WL.sub.i is raised to the High level, V.sub.D +Vt+.alpha. (Vt: threshold voltage of NMOST; and .alpha.: a certain predetermined margin), and data is read from the memory cell 21.sub.i to the bit line BL. As a result, the potential on the bit line BL and the sense amplifier node SA varies by the amount of the read signal from the precharge level (e.g., V.sub.D /2).
At time t1, the control signal PAS is raised to the High level (=V.sub.CC), and the NMOST 81 is turned on, and the n-channel sense amplifier drive common node NS varies to the Low level (=V.sub.SS). At the same time, the NMOST 75 is turned on, and the amplifier 70 is activated, and by virtue of the Low level output of the amplifier 70, the PMOST 80 is turned on, and the p-channel sense amplifier drive common node PS is pulled up to the High level (=V.sub.D). As a result, by the sensing and amplifying action of the p-channel sense amplifier 41 and the n-channel sense amplifier 42, charging and discharging of the pair of the sense amplifier nodes SA, SA and the pair of bit lines BL, BL are commenced.
At time t2, the common node PS reaches the V.sub.D level and the output of the amplifier 70 rises to the High level, and the PMOST 80 is turned off, and supply of electric charge from the main power source voltage V.sub.CC to the p-channel sense amplifier 41 is terminated.
The parasitic capacitance (=RC value) of the pair of bit lines BL, BL is large compared with the parasitic capacitance of the pair of sense amplifier nodes SA, SA. Accordingly, accompanying the rise in the level of one of the bit lines BL, BL having the higher potential (e.g., BL), the level of one of the sense amplifier nodes SA, SA having the higher potential (e.g., SA), and the level of the common node PS are lowered, and the PMOST 80 is again turned on. The PMOST 80 is thus turned on and off repetitively several times, and up to time t4 when the bit line BL having the higher potential reaches the V.sub.D level, electric charge to the p-channel sense amplifier 41 is intermittently supplied.
At time t3, after the potential difference between the pair of sense amplifier nodes SA, SA becomes sufficient, the column decoder output signal CL is raised, and the NMOST 51 and 52 are turned on, and the read data is transferred to the pair of data lines DB, DB. In preparation for rewriting in the memory cell 21.sub.i, the control signal TG is raised to the level of V.sub.D +Vt+.alpha.. Then, at time t4, the potential on the bit lines BL, BL become equal to the potentials on the sense amplifier nodes SA, SA. The data on the sense amplifier nodes SA and SA are thereby rewritten in the memory cell 21.sub.i. The word line is thereafter lowered.
The device of the above-described configuration had the following drawbacks.
(i) In the conventional device, the control signal PAS is raised to the High level at time t1, to activate the current mirror amplifier 70, so that the amplifier 70 is kept activated. The power consumption at the amplifier 70 is therefore large. PA1 (ii) The PMOST 80 is repetitively turned on and off during time t2 to t4, and electric charge is repetitively supplied from the main power source V.sub.CC to the p-channel sense amplifier 41 so time required for completing charging of the bit line BL or BL is long.